a plus make your production a-plus ASM2012CB data sheet a plus integrated circuits inc. address: 3 f-10, no. 32, sec. 1, chenggung rd., taipei, taiwan 115, r.o.c. (115) ???^?? 32 ? 3 ? 10. tel: 886-2-2782-9266 fax: 886-2-2782-9255 website : http: //www.aplusinc.com.tw sales e-mail: mr. jason sales@aplusinc.com.tw technology e-mail: mr. george service@aplusinc.com.tw
ASM2012CB rev 1.0 2002/07/12 1 ASM2012CB ? very low-cost voice synthesize r with 4-bit microprocessor 1.0 general description the am4dd0207 is very low cost voice synthesizer with 4-bit microprocessor. it has various features including 4-bit alu, rom, ram, i/o ports, timers, clock generator, watchdog timer(wdt), voice synthesizer, etc. it consists of 22 instructions in the device. with cmos technology and halt function can mini mize power dissipation. its arch itecture is similar to risc, with two stages of instruction pipe line. it allows all instructions to be executed in a single cycle, except for program branches and data table read instructions (w hich need two instruction cycles). 1.1 feature ? single power supply can oper ate from 2.4v through 5v ? internal program rom: 4k x 10-bit ? 1 sets of 16-bit dpr can access up to 64k x 10 bits data memory space ? data registers: ? 96 x 4-bit data ram (00-1fh plus 40h-7fh) ? unbanked special function registers (sfr) range: 20h-3fh ? i/o ports: ? pra: 4-bit i/o port a (2bh) ? prb: 4-bit output port b (2dh) ? prc: 4-bit input port c (2fh) ? on-chip clock generator: resistive clock drive ( rm) ? timer: 1 ? timer0: a 9-bit auto-reload timer/counter ? stack: 2-level subroutine nesting ? halt and release from halt func tion to reduce power consumption ? watch dog timer ( wdt ) ? instruction: 1-cycle instruction except for t able read and program branches which are 2-cycles ? number of instruction: 22 ? the voice function can be implement ed by microprocessor instruction ? one 8-bit cout output for ASM2012CB
ASM2012CB rev 1.0 2002/07/12 2 figure 1.1 : block diagram of ASM2012CB cout osc vdd/gnd rom 1 pc[11:0] rom latch instruction latch instruction decoder 0 pch(8) pcl(4) pclatch(8) dpr3,2,1 program dlatch(10) clock generator power on reset test select p1,p2,p3,p4 enter test mode timer0(9) reset chip stack ( 12 ) data bus[3:0 ] instruction bus [9:0] rom_addr[15:0] rom_data[9:0] data bus[3:0] control signal addr[15:0] =0000b (addr[15:12]) prasl(4) weak or strong pull-low for pra, (data) instruction bus [9:0] instruction bus [9:0] ( voice synthesizer ) one-channel sram (96 x 4) 40h-7fh (2-level) alu(4) register(4) accumlator ( 4 ) immediate ( 4 ) dpr[15:0] reset pin reset chip pra0 00h-1fh pra(4) prb(4) prc(4) prb, prc cout
ASM2012CB rev 1.0 2002/07/12 3 figure 1.2 : external rom map of ASM2012CB data rom 12bit x 2 stack reset vector 0ffffh(64kx10-bits) 00fffh(4k) 00000h-00fffh pro g ram and data rom 16-bit data pointer pc[11:0] 00000h-0ffffh reserved for testing 00080h-003ffh 00400h 00000h 00080h
ASM2012CB rev 1.0 2002/07/12 4 1.2 pin-out ASM2012CB pin-out prc1 isti std./o.d. input port with programmable strong pull-low or weak pull-low or fix- input-floating capability prc0/reset isti std./o.d. input port with programmable strong pull-low or weak pull-low or fix- input-floating capability mask option selected as an extern al reset pin with weak pull-low capability pra3-1 i/o sti std./o.d. i/o port with programmable strong pull- low or weak pull-low or fix-input- floating capability output type with standard or open-drain output pra0/reset i/o sti std./o.d. i/o port with programmable strong pull- low or weak pull-low or fix-input- floating capability output type with standard or open-drain output mask option selected as an extern al reset pin with weak pull-low capability osc i - rm mode oscillator input vdd1 i - first power supply during operation cout o - current output of audio gnd1 i - first circuit ground potential gnd2 i - second circuit ground potential test o - enter test mode. ( test = high ) vdd2 i - second power supply during operation prb0-3 o std./o.d. output type with standard or open-drain output prc2-3 isti std./o.d. input port with programmable strong pull-low or weak pull-low or fix- input-floating capability 1.3 application circuit
ASM2012CB rev 1.0 2002/07/12 5 1.4 bonding diagram substrate must be connected to gnd. ASM2012CB pad location chip size: x= 1540+80 (um), y=1780+80 (um) pad # pad name x y pad # pad name x y 1 ra3 -682.16 -772.68 11 rb3 674.88 -772.68 2 ra2 -559.84 -772.68 12 osc 633.56 804 3 ra1 -437.52 -772.68 13 test 432.48 804 4 ra0 -315.2 -772.68 14 vdd2 273.16 804 5 vdd1 -191.28 -772.68 15 gnd2 134.68 804 6 cout 71.12 -772.68 16 rc0 -51.76 804 7 gnd1 189.52 -772.68 17 rc1 -248.4 804 8 rb0 307.92 -772.68 18 rc2 -454.24 804 9 rb1 430.24 -772.68 19 rc3 -650.88 804 10 rb2 552.56 -772.68 19 18 17 16 15 14 13 12 rc3 rc2 rc1 rc0 gnd2 vdd2 test osc ASM2012CB ra3 ra2 ra1 ra0 vdd1 cout gnd1 rb0 rb1 rb2 rb3 1 2 3 4 5 6 7 8 9 10 11 ( 64k x 10-bit ) block rom
ASM2012CB rev 1.0 2002/07/12 6 1.5 dc characteristics for ASM2012CB symbol parameter vdd min. typ. max. unit condition vdd operating voltage 2.4 3 5.5 v depending on freq. 31 isb standby 51 ua 4mhz, rm in halt mode 32 iop supply current operating 57 ma 4mhz, rm io floating 33 59 iih input current /internal pull low 5-5.2 ua 4mhz, rm in halt mode (io ports with weak pull-high pull-low) 3-3 ioh output high current 5-8 37 iol output low current 520 34 cout da current out (full scale) 55.2 ma 4mhz, rm (io ports) df/f frequency stability -10 10 % fosc(3v- 2.4v) fosc (3v) df/f fosc variation -20 20 % vdd=3v, rosc=200k, 4mhz figure 1.3 : frequency range for rosc in rm mode resistor(k ohm) 300 200 130 110 3v freq.(mhz) 2.56 3.92 5.48 7.11 rosc & freq. 2.56 3.92 5.48 7.11 0 2 4 6 8 0 100 200 300 400 rosc k ohm freq. mhz
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